comscore Patent applications hint at 3D chip packaging for components in upcoming Apple devices
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Patent applications hint at 3D chip packaging for components in upcoming Apple devices

Apple has long been trying to figure out “2.5D” or even “3D” ways to package the internals on a chip in its search for “significant" performance gains.

  • Published: June 13, 2018 8:50 PM IST

Apple is constantly looking at making improvements in the external as well as the internal design of its devices. These improvements range from the quest to pack a bigger battery, more advanced internal components, and at the same time, occupying smaller space than the older models. This allows the company to push the design to a new benchmark in terms of the thickness of the device along with the freedom to experiment with materials or newer components. The company has long been trying to figure out 2.5D or even 3D ways to package the internals of a chip in its search for significant gains when it comes to areas such as memory bandwidth, larger batteries, and reduced power consumption. Also Read - PUBG New State receives over 17 million pre-registrations as closed alpha testing ends

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One of the latest breakthroughs while making the newer iPhones came when Apple s foundry partner TSMC cracked the integrated fan-out (InFO) innovation. This has lead to improved performance with better thermal management and package height as reported by MacRumors. The report went on to add that this breakthrough has pushed both the companies to further develop its packing offerings. TSMC s efforts in this area have pushed the foundry to the top when it comes to packaging techniques. Even though InFO has not resulted in improved electrical performance, future improvements in how smartphone makers pack the internal components of a smartphone may lead to High Bandwidth Memory or HBM. Also Read - Apple CEO Tim Cook claims iOS is more secure than Android

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This development would be in line with the mention of HBM that we have seen in a number of patents. This type of memory would result in increased number of channels while reducing the total transfer speed between per memory channel. This would result in the overall increase of the bandwidth with a decrease in the energy consumption by the system.

Another thing is the use of interposers, an electrical interface that connects one socket or electrical connection to another. A number of patents hint that Apple may do away with them while working on true 3D techniques where memory will be placed directly on the top on an active SoC. The report points at a patent application that hints at increased coordination between TSMC and Apple for new improvements in the packing. Though there are a number of challenges when it comes to commercializing a true 3D setup ranging from sufficient yield to electrical isolation from radiated energy from other components in the setup. Though, Apple is planning to fix it by shielding the components directly inside the 3D setup.

However, this would also pose challenges in thermal cooling of the package. One of the patents points out that using a carrier substrate is likely to fix some of the issue related to thermal cooling. Considering that there are a number of technical challenges that TSMC and Apple are yet to figure out, it makes it certain that we are years away from true 3D chip packaging but it is good to see Apple already trying to work the problem for improved performance of next-generation devices.

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  • Published Date: June 13, 2018 8:50 PM IST



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